Design of JESD204B High Speed Interface for Waveform Digitization

ZHENG Manyu; CAO Ping; AN Qi

doi:10.11804/NuclPhysRev.34.04.745

At present, due to the wide application of nuclear and particle physics experiments in the waveform digitization technology and the increasing demand of high speed and high accuracy for ADC, the PCB layout is more and more complex and the cost is higher. In order to simplify the design and reduce the cost, this paper put forward the scheme of JESD204B high speed interface for the waveform digitization technology in nuclear and particle physics experiments. Firstly the interface protocol and the demand of JESD204B is introduced. Then the solution based on Altera FPGA and special JESD204B clock chip LMK0482x is proposed. The preliminary test results show that the clock performance is excellent and JESD204B link is functioning normally. Moreover, the system has an excellent performance. The scheme can realize the design of JESD204B high speed interface and therefore be applied to the waveform digitization technology.

Design of JESD204B High Speed Interface for Waveform Digitization

1. State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026;

2. School of Nuclear Science and Technology, University of Science and Technology of China, Hefei 230026

Funds: National Key Research and Development Plan(2016YFA0401602)

Received Date: 2017-03-07

Rev Recd Date: 2017-03-23

Publish Date: 2017-12-20

Key words:

waveform digitization /
JESD204B /
FPGA /
ADC

Abstract: At present, due to the wide application of nuclear and particle physics experiments in the waveform digitization technology and the increasing demand of high speed and high accuracy for ADC, the PCB layout is more and more complex and the cost is higher. In order to simplify the design and reduce the cost, this paper put forward the scheme of JESD204B high speed interface for the waveform digitization technology in nuclear and particle physics experiments. Firstly the interface protocol and the demand of JESD204B is introduced. Then the solution based on Altera FPGA and special JESD204B clock chip LMK0482x is proposed. The preliminary test results show that the clock performance is excellent and JESD204B link is functioning normally. Moreover, the system has an excellent performance. The scheme can realize the design of JESD204B high speed interface and therefore be applied to the waveform digitization technology.

HTML

Reference (10)

[1]	JONATHAN H. China Electronic Market, 2016(6):39. (in Chinese) (JONATHAN H. 中国电子商情:基础电子, 2016(6):39.)
[2]	ANTHONY D, MICHAEL G. Electronic Products, 2013(6):31. (in Chinese) (ANTHONY D, MICHAEL G. 今日电子, 2013(6):31.)
[3]	CHEN Andy. The Needs and Implementation for JESD204B Serial Interface Clock[R]. TI reports, 2014.01. http://www.ti.com.cn/cn/lit/an/zhca591/zhca591.pdf)
[4]	LI Peixian, GUAN Mengyun, YANG Changgen, et al. Chinese Physics C, 2016(11):133.
[5]	Analog Devices, "12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter," AD9234 datasheet, 2017.02.http://www.analog.com/media/en/technicaldocumentation/data-sheets/AD9234.pdf.
[6]	JONATHAN H. China Electronic Market, 2016(6):39. (in Chinese) (JONATHAN H. 中国电子商情:基础电子, 2014(10):39.)
[7]	JONATHAN H. China Electronic Market, 2016(6):39. (in Chinese) (JONATHAN H. 中国电子商情:基础电子, 2013(9):36.)
[8]	ZHOU Dianmiao, XU Hui, CHEN Weihua, et al. Electronic Science and Technology, 2015, 28(10):53. (in Chinese) (周典淼, 徐晖, 陈维华, 等. 电子科技, 2015, 28(10):53.)
[9]	JEDEC Standard JESD204B (July 2011). JEDEC Solid State Technology Association. www.jedec.org/sites/default/files/docs/JESD204B.pdf.
[10]	JESD204B IP Core User Guide (2016.10). Altera Corporation. https://www.altera.com/content/dam/altera-www/global/enUS/pdfs/literature/ug/ugjesd204b.pdf.

Design of JESD204B High Speed Interface for Waveform Digitization

doi: 10.11804/NuclPhysRev.34.04.745

Abstract

References

Proportional views

通讯作者: 陈斌, bchen63@163.com

Article Metrics

Proportional views