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YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
Citation: YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046

Testing of a 12 bit 30 MSPS SAR ADC

doi: 10.11804/NuclPhysRev.35.01.046
Funds:  National Natural Science Foundation of China (11722545); Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27)
More Information
  • Corresponding author: ZHAO Lei, E-mail:zlei@ustc.edu.cn。
  • Received Date: 2017-05-04
  • Rev Recd Date: 2017-06-02
  • Publish Date: 2018-03-20
  • Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation-register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC.
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    [4] LIU Jianfeng, ZHAO Lei, YU Li, et al. Evaluation of a Frontend ASIC Prototype for the Readout of PMTs in Water Cherenkov Detector Array[C]//IEEE International Conference on Electronic Measurement & Instruments, IEEE, 2016:507.
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    [7] Analog Devices, Inc. 12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO, AD9522-3 Data Sheet. Rev. A[EB/OL].[2017-01-19]. http://www.analog.com/en/products/clock-and-timing/clock-generation-distribution/ad9522-3.html.
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Testing of a 12 bit 30 MSPS SAR ADC

doi: 10.11804/NuclPhysRev.35.01.046
Funds:  National Natural Science Foundation of China (11722545); Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27)
    Corresponding author: ZHAO Lei, E-mail:zlei@ustc.edu.cn。

Abstract: Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation-register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC.

YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
Citation: YANG Yunfan, ZHAO Lei, ZHOU Shengzhi, LIU Jianfeng, LIU Shubin, AN Qi. Testing of a 12 bit 30 MSPS SAR ADC[J]. Nuclear Physics Review, 2018, 35(1): 46-52. doi: 10.11804/NuclPhysRev.35.01.046
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