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本测试系统目标为针对PASC ASIC进行系统化的性能测试,以准确评估该芯片时间和电荷测量相关指标,保证PASC能适用于LHAASO WCDA的读出中。此芯片应用指标需求参数具体如表1所列。
项目 指标需求 动态范围 S.P.E.(Single Photoelectron)~ 2 000 P.E.(S.P.E.
约4 mV)电荷分辨精度 <30% @S.P.E., 3%@2 000 P.E. 时间分辨精度 <500 ps RMS -
电荷测量过程需对待测信号的电荷量进行计算并给出电荷测量精度。此过程需要PASC ASIC内部进行滤波成形,并结合PASC外部的ADC电路以及FPGA数字寻峰逻辑完成[6]。对同一电荷量下进行多次测量,其电荷测量结果的RMS值可定义为电荷测量精度,该指标是评估PASC ASIC性能的关键指标。通过示波器虽然可以获取成形后的准高斯波形,但受限于示波器本身的量程和分辨精度,在小信号下无法进行精确的电荷精度测试,因此本论文所设计的测试系统有必要对电荷量进行精确测量。此外我们还需要考虑将芯片和电子学后续电路相结合用于评估整个电子学系统的电荷精度,因此电荷测量方案我们选取了兼容系统读出电子学的整体技术路线[7],即结合FPGA数字寻峰技术。该技术首先采用PASC芯片内电荷成形电路将较快速的PMT输出信号调理成较慢的准高斯信号,其波形的峰值与面积成正比,然后通过中高速ADC芯片将波形进行模数转换,最后将得到的数字化信号输入FPGA计算峰值,峰值即可代表电荷量。通过MATLAB进一步统计和分析计算,得到电荷精度的RMS值,反推出系统的电荷测量精度。
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对于时间测量,则要获取信号到达的时间信息并计算时间测量精度。芯片内部集成了放大、时间甄别电路,PMT输出的模拟信号经过芯片内时间甄别电路后转换为一个数字脉冲,数字脉冲的上升沿即为信号的到达时间。甄别后的信号直接送入测试电路的FPGA中,利用FPGA内部TDC进行时间数字转换,即可得到此芯片用于实际电子学系统的相关指标。在实际测试过程中,仅在需要时使用高速示波器直接观察甄别器输出的数字脉冲信号来判断芯片功能是否正确,性能测试则使用FPGA-TDC进行数字化。基于时钟分相原理的FPGA-TDC占用资源较少且较易于实现,适用于多通道集成。为了扩大TDC的动态范围,同时为了保证较高测量精度,利用粗细结合测量的思想,将16 ns的时钟周期细分为48份,时间测量分辨率可达333 ps,满足应用需求[8]。另外在测试系统连接上,通过延时线法来消除信号源本身的晃动对测量结果的影响,通过功分器提供同步输入信号,计算相邻两通道间时间延迟差的RMS值,反推出系统的时间测量精度。
Design of Front-end Chip Batch Test System for LHAASO WCDA
doi: 10.11804/NuclPhysRev.37.2020024
- Received Date: 2020-04-19
- Rev Recd Date: 2020-05-21
- Publish Date: 2020-07-15
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Key words:
- LHAASO WCDA /
- ASIC /
- automatic testing /
- charge measurement /
- time measurement
Abstract: In the readout electronics for the Water Cerenkov Detector Array(WCDA) of the Large High Altitude Air Shower Observatory(LHAASO), both high precision time and charge measurement are required. A front-end readout chip PASC(Pre-Amplifier and Shaping Circuit) ASIC(Application Specific Integrated Circuit)is designed, and will be actually applied in the third water pond of the WCDA. In order to evaluate the performance of the chips after massive production, it is important to design an automatic test system. This paper presents the design of the ASIC test system, which is used to achieve automatic testing of the time and charge measurement performance of the chips. After a brief introduction of the chip under test, the design scheme and structure of the test system is presented, including the hardware circuits and test software. This system has been applied in batch test of the LHAASO project, and 100 chips have been successfully tested. It can communicate with multiple instruments through the central control software to perform instrument control and complete automated testing and data recording. This automated test method is more suitable for performance testing and evaluation of high precision readout chips under a large dynamic range, which greatly simplifies the test process and can greatly improve the work efficiency of a large number of repetitive test steps in batch test. The test results show that the performance of these chips meet the application requirements of the third pond of the WCDA in LHAASO.
Citation: | Dexian WANG, Lei ZHAO, Zhen GONG, Ruoshi DONG, Zhe CAO, Shubin LIU, Qi AN. Design of Front-end Chip Batch Test System for LHAASO WCDA[J]. Nuclear Physics Review, 2020, 37(2): 191-198. doi: 10.11804/NuclPhysRev.37.2020024 |