Fengshou TIAN, Lei ZHAO, Yichun FAN, Jiajun QIN, Longwei LAI, Shubin LIU, Qi AN. Design of High-repetition-rate Beam Sampling Processor Prototype[J]. Nuclear Physics Review, 2021, 38(4): 402-409. doi: 10.11804/NuclPhysRev.38.2021020
Citation:
|
Fengshou TIAN, Lei ZHAO, Yichun FAN, Jiajun QIN, Longwei LAI, Shubin LIU, Qi AN. Design of High-repetition-rate Beam Sampling Processor Prototype[J]. Nuclear Physics Review, 2021, 38(4): 402-409. doi: 10.11804/NuclPhysRev.38.2021020
|
Design of High-repetition-rate Beam Sampling Processor Prototype
-
Fengshou TIAN1, 2
,
,
-
Lei ZHAO1, 2
,
,
,
-
Yichun FAN1, 2
,
-
Jiajun QIN1, 2
,
-
Longwei LAI3
,
-
Shubin LIU1, 2
,
-
Qi AN1, 2
- 1.
State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei 230026, China
- 2.
Department of Modern Physics, University of Science and Technology of China, Hefei 230026, China
- 3.
Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai 201204, China
Funds:
Knowledge Innovation Program of the Chinese Academy of Sciences(KJCX2-YW-N27); Youth Innovation Promotion Association, Chinese Academy of Sciences
More Information
- Corresponding author:
E-mail: zlei@ustc.edu.cn.
- Received Date: 2021-03-08
- Rev Recd Date:
2021-04-20
- Publish Date:
2021-12-20
-
Abstract
In order to sample and process the signal of the Shanghai High Repetition Rate XFEL and Extreme Light Facility (SHINE) strip-line BPM system, a prototype of High-Repetition-Rate Beam Sampling Processor was developed. The processor has four channel input, 1 GSps maximum sampling rate and 16 bit resolution. It adopts Xilinx Zynq series FPGA with embedded ARM core, which can run Linux operating system and realize readout of high-speed sampled-data and data buffering. The processor adopts the structure of mother board and daughter board. The daughter board with ADC is for data sampling, and the mother board with FPGA is used to process the digital data. The daughter board and the mother board transmit data through the FMC interface. The ADC uses JESD204B protocol to transmit data, and the maximum total data rate is 80 Gbps through 16 pairs of differential channels. First the ADC data is transmitted to the digital motherboard. Then it is buffered by FIFO and DDR and finally transmitted to the upper computer for processing and analysis through the RJ45 interface with TCP/IP protocol. The data rate of RJ45 interface is about 900 Mbps. After testing, the bandwidth of ADC daughter board is higher than 480 MHz, and the ENOB(effective number of bits) is higher than 10-bit in 480 MHz bandwidth. The FPGA digital mother board runs Linux compiled by Petalinux, which can realize the data storage and transmission of 1 M sampling points of four channels in continuous or trigger mode. The processor can meet the design requirements.
-
References
[1]
|
LAI Longwei, LENG Yongbin, YI Xing, et al. Nuclear Science and Techniques, 2011, 22(3): 129. doi: 10.13538/j.1001-8042/nst.22.129-133 |
[2]
|
冷用斌, 周伟民, 袁任贤, 等. 核技术, 2010, 33(6): 401. doi: CNKI:SUN:HJSU.0.2010-06-002
LENG Yongbin, ZHOU Weimin, YUAN Renxian, et al. Nuclear Techniques, 2010, 33(6): 401. (in Chinese) doi: CNKI:SUN:HJSU.0.2010-06-002 |
[3]
|
冷用斌, 易星, 赖龙伟, 等. 核技术, 2011, 34(5): 326. doi: CNKI:SUN:HJSU.0.2011-05-004
LENG Yongbin, YI Xing, LAI Longwei, et al. Nuclear Techniques, 2011, 34(5): 326. (in Chinese) doi: CNKI:SUN:HJSU.0.2011-05-004 |
[4]
|
张雪萍, 童子权, 任丽军, 等. 国外电子测量技术期刊, 2006, 25(9): 12.
ZHANG Xueping, TONG Ziquan, REN Lijun, et al. Foreign Electronic Measurement Technology, 2006, 25(9): 12. (in Chinese) |
[5]
|
Texas Instruments. LMK04832 Datasheet[EB/OL]. [2021-03-20]. www.ti.com.cn/cn/lit/ds/symlink/lmk04832.pdf. |
[6]
|
Xilinx. Zynq UltraScale+ MPSoC Technical Reference Manual(UG1085) [EB/OL]. [2021-03-20]. www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf. |
[7]
|
Xilinx. DC and AC Switching Characteristics(DS925)[EB/OL]. [2021-03-20]. www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf. |
[8]
|
石蕾. TD-LTE基站中数字中频系统的设计及FPGA实现[D]. 武汉: 武汉科技大学, 2015.
SHI Lei. Design and FPGA Implementation of Digital Intermediate Frequency System in TD-LTE Base Station[D]. Wuhan: Wuhan University Of Science And Technology, 2015. (in Chinese) |
[9]
|
樊周华. 基于JESD204B标准的高速串行接口设计与实现[D]. 西安: 西安电子科技大学, 2015.
FAN Zhouhua. A Study of High-speed Serial Interface Based on JESD204B Standard[D]. Xi’an: Xidian University, 2015. (in Chinese) |
[10]
|
Xilinx. JESD204 PHY v2.0 LogiCORE IP Product Guide (PG198)[EB/OL]. [2021-03-20]. http://www.xilinx.com/support/documentation/ip_documentation/jesd204_phy/v3_0/pg198-jesd204-phy.pdf. |
[11]
|
Xilinx. JESD204 v6.1 LogiCORE IP Product Guide (PG066) [EB/OL]. [2021-03-20]. http://www.xilinx.com/support/documentation/ip_documentation/jesd204/v6_2/pg066-jesd204.pdf. |
-
-
Proportional views
-