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设计的LDO采用国产GSMC 130 nm CMOS工艺,整个版图的面积大小仅103.5 μm×95.2 μm。如图8所示,其中面积占比最大的部分是补偿电容,位于版图下方,其次是偏置电路中的电阻,位于右上方,CMOS晶体管位于版图左上侧,其外围是一圈保护环,保护环不仅可以消除单粒子闩锁的影响,还能够抗总剂量效应[12] ,减小辐射的影响。
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设计的LDO的输出电压为1.2 V,输入动态范围为2.4~3.6 V。LDO的静态电流为8.5
$ {\text{μA}} $ ,最大负载电流为20 mA。版图设计完成后,对LDO进行性能仿真(所有仿真均在负载电容为100 pF下进行),线性调整率如图9所示,仿真结果表明,在负载电流为0 mA和20 mA时,线性调整率分别为3.2,3.3 mV/V。负载调整率如图10所示,在输入电压为3 和3.6 V 时的负载调整率分别为256, 266$ {\text{μV}} $ /mA。LDO的负载瞬态响应波形见图11,当输出电流在100$ {\text{μ A}} $ 至20 mA之间跳变时,过冲和下冲电压约为100 mV,恢复时间分别为3.5$ {\text{μs}} $ 、900 ns。LDO在各工艺角下仿真的输出电压情况如表1(输入电压为2.5 V,负载为100 pF),由图可知输出电压在ss工艺角下最小,在ff工艺角下达到最大,这是由于ss工艺角下阈值电压高,功率管的源漏电压大,导致输出电压偏低,ff工艺角下阈值电压低,功率管的$ {V_{{\text{ds}}}} $ 较小,因此输出电压偏高,但误差都在芯片可正常工作范围内。温度(°C) 负载电流为100 $ {\text{μA}} $时
的输出电压/V负载电流为20 $ {\text{mA}} $时
的输出电压/Vss tt ff ss tt ff −40° 1.199 1.201 1.206 1.195 1.197 1.201 27° 1.199 1.201 1.207 1.194 1.197 1.201 125° 1.195 1.199 1.205 1.189 1.193 1.199 负载调整率 −0.96%~+0.58% 表2为本文与其他已发表文献设计的无片外电容LDO的主要性能参数对比,表中的稳定时间、过冲与下冲电压等性能参数是输入电压为2.5 V,负载为100 pF时的后仿真结果。由表2可看出与文献[15-17]对比,设计的LDO具有最低的静态电流,过冲电压也较小,因此设计的无片外电容LDO在低功耗下依然具有较强的瞬态响应。
A Low Power and Strong Transient Response LDO Circuit
doi: 10.11804/NuclPhysRev.40.2022071
- Received Date: 2022-06-16
- Rev Recd Date: 2022-08-15
- Available Online: 2023-12-07
- Publish Date: 2023-09-20
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Key words:
- CEE /
- readout electronics /
- lip voltage follower(FVF) /
- low dropout linear regulator(LDO)
Abstract: A large number of pixel sensor chips are integrated on the beam detector in CEE experiment, in order to provide stable power voltage for these chips, and meet the high requirements of silicon pixel chips for small area and low power consumption of power supply circuit, a low voltage differential linear regulator(Low-dropout regulator, LDO) circuit compensated by a single Miller capacitor is realized in 130 nm CMOS process of GSMC. The proposed LDO based on the flip voltage following(Flipped Voltage Follower, FVF) structure which can achieve high stability, fast transient performance and ultra-low power consumption when the load current changes rapidly, and does not require off-chip capacitance when using small transistors. The experimental results show that the structure can drive a capacitive load of 0~100 pF when the load current is 20 mA, the line regulation is 3.3 mV/V, the quiescent current is 8.5 μA, and the layout area is only 103.5 μm×95.2 μm, which is suitable for highly complex detector system chips.
Citation: | Jiajia LIU, Qingwen YE, Ping YANG. A Low Power and Strong Transient Response LDO Circuit[J]. Nuclear Physics Review, 2023, 40(3): 433-438. doi: 10.11804/NuclPhysRev.40.2022071 |