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利用TCAD仿真工具构建了SiC双沟槽MOSFET器件模型,截面示意如图1所示。外延层厚度为9 μm,掺杂浓度为3×1015 cm−3,用于器件单粒子效应加固的缓冲层厚度为1.5 μm,掺杂浓度为3×1017 cm−3,其击穿特性曲线如图2所示,击穿电压为1 512 V。因此,本次模拟选取的偏置电压均低于1 512 V,器件的详细参数如表1所列。
参数 值 单个器件宽度/μm 5.7 N-漂移区深度/μm 9 N-漂移区掺杂浓度/cm−3 3×1015 衬底深度/μm 150 源/栅极沟槽深度/μm 1.55 源/栅极沟槽宽度/μm 2 栅氧化层厚度/nm 50 N+源极深度/μm 0.2 N+源极和衬底掺杂浓度/cm−3 1×1019 N+缓冲区深度/μm 1.5 N+缓冲区掺杂浓度/cm−3 3×1017 P-基区深度/μm 0.5 P-基区掺杂浓度/cm−3 2×1017 P型区域深度/μm 1.8 P型区宽度/μm 1.35 P型区掺杂浓度/cm−3 2×1018 本论文采用TCAD软件开展SiC双沟槽MOSFET器件的单粒子烧毁效应模拟研究,根据Mcpherson等[11]对SiC材料中与电热效应相关的导热系数、热阻和热容参数进行修正,热导率、热阻和热容分别表示为
其中:T为SiC的晶格温度;
$\alpha _1 $ =−1.882 2×10−1 cm∙K/W;$\beta_1 $ =1.636 7×10−3 cm/W;$\gamma_1 $ =−1.694 1×10−20 cm/(W∙K) ;$\alpha _2 $ =1.577 8×100 J/(K∙cm3) ;$\beta_2 $ =3.533 2×10−3 J/(K2∙cm3);$\gamma_2 $ =−1.544 7×10−6 J/(K3∙cm3);μ2=2.605 2×10−10 J/(K4∙cm3)。 -
采用器件仿真软件Sentaurus TCAD[8]开展重离子辐照SiC双沟槽MOSFET器件的SEB效应模拟计算。其中采用了重离子辐照模型,具体原理如下:当重离子穿透一个半导体器件时,它会损失能量,并沿入射径迹产生一系列的电子-空穴对,这些额外的电子和空穴可能会形成足够大的电流来影响器件的运行状态。由重离子引起的电子-空穴对的生成率表示为
其中:R(w,l)和T(t)分别为描述电子空穴对产生率的时空变化的函数;GLET(l)是线性能量转移(LET)[12-14]的产生密度;l表示离子径迹长度,设置为11 μm,其长度贯穿该器件的寄生晶体管,使寄生晶体管更易导通;w为离子径迹半径,决定电子空穴对的产生范围,本工作离子径迹半径w设置为0.03 μm[8]。LET值设置为0.1 pC/μm[8]。重离子入射产生的电子-空穴对数在4 ps时达到峰值[8]。
值得注意的是,二维模拟不同于三维模拟,离子入射产生的电子空穴对在器件中的空间分布是薄片状而非圆柱状,因此,本文为定性而非定量研究。本模拟工作基于禁带宽度变窄(BGN)模型、肖克利-里德霍尔(SRH)复合模型、俄歇复合模型、雪崩击穿模型等物理模型[2],还考虑了SiC材料的不完全电离和各向异性[15],对于晶格温度的计算,使用了热力学模型[15],用于计算器件内部非均匀分布的晶格温度。
由于SiC双沟槽MOSFET的结构呈轴对称性,本工作选择了该器件的半个单元结构进行单粒子烧毁效应的仿真研究,并对SiC双沟槽MOSFET器件的模拟模型进行网格化处理。仿真选取的重离子入射位置如图3所示,此处靠近器件内部寄生晶体管的所在位置,产生的电子空穴对更易造成寄生晶体管导通,更容易诱发单粒子烧毁效应[8]。由于SiC的熔点一般在2 900至3 100 K范围内[9],本工作设定SiC双沟槽MOSFET器件发生单粒子烧毁效应的临界温度为3 000 K。
Simulation Study on Single-Event Burnout Effect in SiC DT-MOSFET
doi: 10.11804/NuclPhysRev.40.2022106
- Received Date: 2022-10-13
- Rev Recd Date: 2022-12-05
- Publish Date: 2023-09-20
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Key words:
- SiC DT-MOSFET /
- single event effect /
- single event burnout /
- lattice temperature
Abstract: SiC DT-MOSFET are prone to single event burnout(SEB) effect under heavy ion incident conditions. In this work, the TCAD program is used to simulate and calculate the spatial distribution of physical quantities such as drain curren, current densityt, lattice temperature, collision ionization and power density inside the device, and evaluate the influence of bias voltage on SEB effect. According to the simulation results, the transient current source formed by the incident ions turns on the parasitic bipolar transistor, the high drain source voltage maintains the avalanche effect in the device, and then the positive feedback mechanism of the device is established. Finally, the generated transient high current leads to the thermal damage of the device. Therefore, the main cause of SEB effect in SiC DT-MOSFET is the conduction of parasitic bipolar transistor and the establishment of positive feedback mechanism. In addition, the effect of strong electric field on collision ionization, lattice temperature and power density distribution is evaluated, and the reason why the peak region of power density corresponds to the peak region of lattice temperature is revealed, which provides data support for the anti nuclear reinforcement technology of SiC DT-MOSFET.
Citation: | Jinqiu PENG, Hang ZHANG, Kang WU, Xingyu LIU, Xu YANG, Xiaohou BAI, Zheng WEI, Zeen YAO, Junrun WANG, Tianzhi JIANG, Chao BAO, Jiawei LU, Yu ZHANG. Simulation Study on Single-Event Burnout Effect in SiC DT-MOSFET[J]. Nuclear Physics Review, 2023, 40(3): 459-465. doi: 10.11804/NuclPhysRev.40.2022106 |